The present invention relates generally to the field of integrated circuits and, in particular, to a method for forming gate segments for an integrated circuit
In the integrated circuit industry, designers continuously try to put more circuitry onto a given surface area of semiconductor material. The goal is to provide integrated circuits that can perform more functions without increasing the size of the circuit. To do this, designers develop techniques to pack the elements of the circuits closer together on the semiconductor material. Thus from generation to generation, an integrated circuit has a higher density of circuit elements and can perform more sophisticated functions. This can readily be observed in the case of microprocessors for personal computers.
In many instances, this increase in density follows well defined trends. For example, in the area of memory devices, the size of the cells that store the data for the memory device decrease by approximately one-third in each successive generation. Many factors contribute to this trend. For example, semiconductor processing typically uses lithographic techniques. These techniques impose a minimum dimension for creating circuit elements that is referred to as the minimum xe2x80x9clithographic dimension.xe2x80x9d By creating improvements in the tooling used for the lithography, designers continuously improve the minimum lithographic dimension. This follows a well defined pattern such that the minimum lithographic dimension for the next generation of memory devices can be predicted with some degree of accuracy. Other factors also contribute to the trend in the size of these memory cells.
At present, designers are working on ways to produce high density dynamic random access memory devices (DRAMs) in the gigabyte range. To stay on course with the traditional industry trend, each cell of the next generation memory device will be on the order of 0.25 xcexcm2 with a minimum lithographic dimension of approximately 0.18 xcexcm. One conventional layout for a DRAM device is referred to as a folded bit line layout Each cell in the folded bit line layout requires 8 xe2x80x9cfeatures.xe2x80x9d A feature is traditionally one-half of the dimension of a word or bit line xe2x80x9cpitch.xe2x80x9d The term xe2x80x9cpitch refers to the line plus required spacing. This feature size limitation dictates that a folded bit line layout requires a minimum of 8 feature sizes. It can be seen that decreases in the minimum dimension alone will not allow the cell size to continue to follow these well defined industry trends.
Designers have created a partial solution to this problem. They have replaced traditional word lines with sub-lithographic word lines that are formed outwardly from segmented gates regions of access transistors in each cell. The dimension of the word line that is normal to the surface of the substrate is greater than the width of the word line. One problem with this technique involves formation of the gate segments.
U.S. Pat. No. 5,539,229, entitled xe2x80x9cMOSFET with Raised STI Isolation Self-Aligned to the Gate Stackxe2x80x9d describes a gate oxide and conductor layer that are formed prior to formation of the shallow trench isolation that separates the cells of the memory device. The gate areas are formed next by removing portions of the conductor layer that cover the source and drain regions of the cell. The disadvantage of this technique is that the gate oxide and surface doping implant profiles are exposed to the mechanical and thermal processing associated with forming the shallow trench isolation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method for forming gate segments for an integrated circuit without inadvertently affecting the doping implant profiles of the transistors or the gate oxide.
The above mentioned problems with forming gate segments for an integrated circuit and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A method for forming gate segments for an integrated circuit is described in which the gate segments are formed after the shallow trench isolation so as to avoid exposing the source/drain implants and gate oxide to the chemical/mechanical processes associated with formation of the shallow trench isolation. Further, by forming the shallow trench isolation regions first, the gate segments are self aligned to the active regions.
In particular, an illustrative embodiment of the present invention includes forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.